Mobility Models and Middleware Support for Mobile AdHoc Networks

Motahhareh Moravvej Hamedani

Embedded systems are increasingly expected to provide good performance at low cost. As the characteristics of compiled code can have an impact on the overall cost of an embedded system, a compilation strategy must be cost aware as well as achieve high performance. As one major factor for system cost is their execution time. On the other hand, code size is an important issue due to limited memory of some embedded systems. Thus, cost-effective optimization strategies that are able to perform a good trade-off between code size and performance improvement are needed. Mobile ad-hoc networks (MANETs) are random, self-configurable and rapidly deployable networks without any infrastructure.  The data is moved between the memory and these registers by means of Load and Store instructions. The word length of the Nios II processor is 32 bits. All registers are 32 bits long. Byte addresses in a 32-bit word are assigned in little-endian style, in which the lower byte addresses are used for the less significant bytes of the word. The Nios II architecture uses separate instruction and data buses, which is often referred to as the Harvard architecture. In this paper, we review some existed mobility models of ad-hoc network and compare such methods with each other. Also, at the end of this paper, we will suggest new novel model, which has more optimality in comparison with the existed models.

Published on the web: 2018-09-25
Received : 2018-07-15
Submitting : 2018-06-14

Keyword:1- Chipset design
Keyword:2- VLIW Processor
Keyword:3- Code generation parameter.

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